1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated integrated circuits including transistor structures of different threshold voltages.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to increase the number of transistor elements in order to enhance performance of modern CPUs and the like with respect to operating speed and functionality. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, which may also be referred to as a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. For example, so-called short channel effects may occur for highly scaled transistor elements, resulting in a reduced controllability of the channel region, which may result in increased leakage currents and generally in degraded transistor performance. One challenging task in this respect, therefore, is the provision of appropriately designed junction regions in the form of shallow junctions, at least at the area in the vicinity of the channel region, i.e., source and drain extension regions, which nevertheless exhibit a moderately high conductivity so as to maintain the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions at a relatively low level while also controlling the parasitic drain/source capacitance and the electric field of the cut-off region. The requirement for shallow junctions having a relatively high conductivity while providing adequate channel control is commonly met by performing an ion implantation sequence on the basis of a spacer structure so as to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure, and therefore one or more anneal cycles are typically required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage. However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability in turn is limited by the solid solubility of the dopants in the silicon crystal and the temperature and duration of the anneal process that are compatible with the process requirements. Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a “blurring” of the dopant profile. This effect may be advantageous in some cases for defining critical transistor properties, such as the overlap between the extension regions and the gate electrode. Therefore, for highly advanced transistors, the positioning, shaping and maintaining of a desired dopant profile are important properties for defining the final performance of the device, since the overall series resistance of the conductive path between the drain and source contacts as well as the controllability of the channel region may represent a dominant aspect for determining the transistor performance.
Moreover, other important transistor characteristics may presently also be adjusted on the basis of the complex dopant profile in the active regions of the transistor elements. For example, the threshold voltage of a transistor, i.e., the voltage applied between the gate electrode and the source terminal of the transistor element, at which a conductive channel forms in the channel region, is a transistor characteristic that substantially affects overall transistor performance. Typically, the ongoing shrinkage of critical dimensions of the transistors may also be associated with a continuous reduction of the supply voltage of electronic circuitry. Consequently, for performance-driven transistor elements, the corresponding threshold voltage may also have to be reduced in order to obtain a desired high saturation current at a reduced gate voltage, since the reduced supply voltage may also restrict available voltage swing for controlling the channel of the transistor. However, the reduction of the threshold voltage, which may typically be accomplished by appropriately doping the well region of the transistor in combination with sophisticated halo implantation processes, which are designed to provide the appropriate dopant gradient at the PN junctions and the overall conductivity of the channel region, may also affect the static leakage currents of the transistors. That is, by lowering the threshold voltage, typically, the off current of the transistors may increase, thereby contributing to the overall power consumption of an integrated circuit, which may comprise millions of corresponding transistor elements. In addition to increased leakage currents caused by extremely thin gate dielectric materials, the static power consumption may result in unacceptable high power consumption, which may not be compatible with the heat dissipation capabilities of integrated circuits designed for general purposes. In an attempt to maintain the overall static leakage currents at an acceptable level, complex circuitries are typically designed so as to identify speed-critical paths and selectively form transistors of the speed critical-paths to have a low threshold voltage, while less critical signal paths may be realized on the basis of transistors of higher threshold voltage, thereby reducing static leakage currents while, however, also reducing switching speed of these transistors. For example, in modern central processing units (CPUs), several different “flavors” of transistors may be employed in order to take into consideration the different hierarchy with respect to signal processing speed. Consequently, during the complex implantation sequence for defining the dopant profile in the active regions of the transistors of different threshold voltage, an appropriate masking regime may be implemented in order to perform implantation processes on the basis of appropriately selected process parameters, in particular during the corresponding well implantation processes and halo implantation processes in combination with the shallow extension implantations to comply with the various design requirements with respect to implementing transistors of different threshold voltage. Although significant advances have been made with respect to obtaining a desired total performance of complex integrated circuits, while nevertheless not unduly increasing the overall static power consumption, it is nevertheless the goal of semiconductor manufacturers to increase performance of transistors, in particular of low threshold transistors, that is, to increase the drive current substantially without increasing the static leakage currents. In this respect, it has been proposed to enhance transistor performance for transistors by increasing the Miller capacitance by increasing the overlap of the drain and source extension regions with gate electrode structure. Although this concept may be a promising approach for enhancing transistor performance, an efficient implementation in well-established CMOS technologies may have to be realized.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.